In the manufacture of integrated circuits, copper metal interconnects are generally used to couple various electronic devices such as transistors and capacitors. Copper interconnects are often formed using a damascene process whereby a dielectric layer is etched to form a trench into which the copper metal is deposited. The copper deposition is typically followed by a chemical mechanical polishing step to planarize the interconnect and remove excess material.
Prior to the copper metal deposition, a barrier layer, an adhesion layer, and a seed layer must be deposited into the trench in the dielectric layer. The barrier layer prevents the copper metal from diffusing into the dielectric layer. The adhesion layer binds the barrier to the seed. The seed layer provides a surface that enables the copper metal to deposit and adhere within the trench. Metal nitride films, such as tantalum nitride (TaN), may be used to form the barrier layer, while metal layers, such as a tantalum layer (Ta), may be used to provide the adhesion layer for the copper seed layer. As is well known in the art, a TaN/Ta stack is usually deposited into the trench prior to the copper metal. In some applications, a pure Ta layer may be used to provide the barrier and adhesion functionality.
Current chemical vapor deposition (CVD) and atomic layer deposition (ALD) methods for generating a barrier layer and an adhesion layer suffer from many drawbacks. Conventional methods to generate a metal nitride barrier layer employ precursor functionalities that contain problematic amine or imine compounds.
Conventional methods for generating barrier and adhesion layers involve two separate layers, such as the TaN/Ta stack 100 shown in FIG. 1. The TaN/Ta stack 100 typically lines a trench 102 within a dielectric layer 104. Within the trench 102 and atop the TaN/Ta stack 100 are a seed layer 106 and a copper metal interconnect 108. As interconnect widths are scaled down and the trenches 102 become narrower, the stacked TaN/Ta layers 100 will occupy more of the volume within the trench 102. This leaves less room for the seed layer 106 and the copper metal interconnect 108. A point will be reached where there will no longer be sufficient room for the copper metal to be deposited. Thinner barrier and adhesion layers are needed to continue the scaling down of integrated circuit dimensions. Unfortunately, the materials currently used for ALD deposited barrier layers and adhesion layers, such as the TaN/Ta stack 100, may not be extendable due to the previously discussed photolithography implications.
Current methods of forming barrier layers also suffer from other problems. High resistivity interfacial layers such as tantalum oxide may result from known processes. Current methods also make use of corrosive precursors and/or by-products such as halides that can complicate tool design and increases costs. Accordingly, processes are needed to form barrier and adhesion layers that may be used in scaled down integrated circuits without the shortcomings highlighted above.